1. Field of the Invention
The present invention relates to a substrate having a semiconductor layer, and a method for fabricating the same, and in particular to such a substrate having a thin-film semiconductor layer.
2. Description of the Related Art
Thin film transistor (abbreviated as TFT, hereinafter), typically used for a display control of a liquid crystal display apparatus, is formed in a so-called SOI (Silicon On Insulator) layer, that is, a semiconductor layer provided on an insulating layer. FIG. 3 is a sectional view showing an exemplary process for fabricating a substrate having an SOI layer (referred as SOI substrate, hereinafter) by the bonding method. An exemplary fabricating process thereof will be explained referring to the drawing.
First, as shown in FIG. 3A, a semiconductor substrate 101 (e.g., single crystalline silicon substrate) is etched on its first plane 101a using a resist pattern (now shown) as a mask, thereby to form recesses 103. The recesses 103 are made so as to have a depth equivalent to the thickness of an SOI layer to be formed later, so that the recesses 103 are made into approx. 100 nm thick for a desired thickness of the SOI layer of 100 nm. Next, the resist pattern is removed, and an insulating layer 104 (e.g., silicon oxide film) is then formed on the first plane 101a of the semiconductor substrate 101 so as to also fill up the recesses 103.
Next, as shown in FIG. 3B, the insulating layer 104 is polished to make a plane surface 104a, and then, as shown in FIG. 3C, a base substrate 105 is bonded onto the surface of the insulating layer 104.
Next, as shown in FIG. 3D, the semiconductor substrate 101 is lapped from its second plane 101b (opposing to the first plane 101a) to an extent not exerting damage to the surface portion along the first plane 101a, which later remains as an SOI layer, or the semiconductor substrate 101 is delaminated at a predetermined depth from the second plane 101b by the hydrogen implanting separation method.
For the case that the separation is effected by lapping, damage ascribable to the lapping is removed by polishing the semiconductor substrate 101 from the second plane 101b and then by etching by the plasma scanning method, thereby the semiconductor substrate 101 is finished so as to have a uniform thickness over the projected portion of the insulating layer 104.
Thereafter, as shown in FIG. 3E, the semiconductor substrate 101 is polished from the second plane 101b until the insulating layer 104 is exposed, thereby to leave, as an SOI layer 108, the semiconductor substrate 101 only in recesses 107 of the insulating layer 104. Here proceeded is a selective polishing ensuring a high selectivity of the semiconductor substrate 101 over the insulating layer 104. Thus an SOI substrate having on the insulating layer 104 the SOI layer 108 of approx. 100 nm thick is obtained.
In recent years, there has been growing demands for a higher integration, lower power consumption, higher voltage resistance and higher radiation resistance of semiconductor devices, which require further thinning of the SOI layer 108 to satisfy the above demands in TFT.
The method for fabricating the SOI substrate as described above is, however, disadvantageous in that, in the step for selectively polishing the semiconductor substrate 101 as shown in FIG. 3E, the semiconductor substrate 101 has to be over-polished to thoroughly expose the insulating layer 104 over the entire surface of the polishing plane. The over-polishing will thus proceed excessively in the area including the insulating layer 104 exposed earlier than the other area due to non-uniformity in the polishing rate as shown in FIG. 4, which will result in so-called dishing xe2x80x9cAxe2x80x9d in which the surface level of the semiconductor substrate 101 becomes lower than that of the insulating layer 104. Even when the semiconductor substrate 101 is polished at a uniform rate over the entire polishing plane, such dishing xe2x80x9cAxe2x80x9d is also likely to occur in the recess of the insulating layer 104 having larger opening area as shown in FIG. 5 due to an excessive over-polishing after the insulating layer 104 is exposed.
To prevent such dishing xe2x80x9cAxe2x80x9d, chemical polishing without using abrasive grain is employed in some cases in the step corresponded to FIG. 3E. Such chemical polishing will successfully reduce the dishing xe2x80x9cAxe2x80x9d since the polishing of the semiconductor substrate 101 will stop upon the exposure of the insulating layer 104. Surface roughness of thus polished plane, however, increases as compared with that obtained by polishing using abrasive grain.
Substantially no problem will arise from such dishing nor surface roughness of the polished plane as for devices using an SOI layer of approx. 100 to 200 nm thick (typically for the TFT generation of a wiring width of 0.25 xcexcm or below). It is however anticipated that degraded accuracy in the thickness or degraded crystal form of the SOI layer due to the dishing or surface roughness of the polished plane will adversely affect characteristics of devices using an SOI layer having a thickness as thin as 50 nm or below (typically for the TFT generation of a wiring width of 0.1 xcexcm or narrower), and thus ruin the reliability of the devices.
It is therefore an object of the present invention to provide a substrate having a semiconductor layer fabricated by new method for fabricating a substrate having a semiconductor layer. It is another object of the present invention to provide a new method for fabricating a substrate having a semiconductor layer allowing thinning of the semiconductor layer while ensuring accuracy in its thickness and a small surface roughness.
A method for fabricating a substrate having a semiconductor layer of the present invention for achieving the foregoing object is proceeded as follows: first, provided is a patterning step in which a semiconductor layer formed on an insulating layer having recesses is polished to leave the semiconductor layer only in the recesses; next, provided is an etching step in which the insulating layer is etched using the residual semiconductor layer as an etching mask to reduce the depth of the recesses; and further provided is a thinning step in which the semiconductor layer is polished while ensuring a selectivity over the insulating layer to reduce the thickness of the semiconductor layer. In the patterning step of this fabrication method, the semiconductor layer is chemically polished using the insulating layer as a stopper. In the thinning step, the semiconductor layer is polished by chemical mechanical polishing while ensuring a selectivity thereof over the insulating layer.
According to such fabrication method, the semiconductor layer is left in the recesses of the insulating layer by polishing in the patterning step, the insulating layer is then etched to reduce the depth of the recesses, and the semiconductor layer projected out from the recesses is selectively polished off in the thinning step, so that the polishing in the individual steps is targeted only at the portion of the semiconductor layer projected from the surface of the insulating layer. Thus the polishing is performed so as to level the insulating layer and semiconductor layer, without requiring excessive polishing at a time in order to thin the semiconductor layer to a predetermined thickness. This suppresses non-uniform polishing and the resultant local dishing.
In the patterning step, since the semiconductor layer is polished by the chemical polishing using the insulating layer as a stopper, so that the polishing of the semiconductor layer stops upon the exposure of the insulating layer into the polishing plane and dishing due to the over-polishing is prevented from occurring. In the successive thinning step, since the semiconductor layer is polished by chemical mechanical polishing while ensuring a selectively thereof over the insulating layer, so that the polishing of the semiconductor layer can proceed with the insulating layer being exposed. In such chemical mechanical polishing, surface roughness produced on the semiconductor layer during the chemical polishing in the patterning step will successfully be removed. Here the over-polishing is unnecessary since the polishing is targeted at the already-patterned semiconductor layer, which is beneficial in preventing dishing from occurring on the polishing plane.
According to the present invention, thinning of the semiconductor layer on the insulating layer having the recesses is effected by plural times of polishing interposed by the etching of the insulating layer, where polishing amount at a time being limited, so that non-uniform polishing and the resultant local dishing are suppressed. The dishing due to over-polishing in the patterning step for exposing the insulating layer can also be suppressed by chemically polishing the semiconductor layer using the insulating layer as a stopper. The successive thinning step, in which the already-patterned semiconductor layer is selectively processed by chemical mechanical polishing, can prevent the semiconductor layer from being over-polished and thus prevent the resultant dishing from occurring, and can eliminate the surface roughness due to the chemical polishing in the patterning step.
Thus the semiconductor layer can be thinned while ensuring accuracy in its thickness and a small surface roughness. This allows device fabrication in a semiconductor layer formed as thin as 50 nm or below, for example, and device characteristics will not adversely be affected by accuracy in the thickness nor surface roughness, so that the device will be kept highly reliable.